1. Field of the Invention
The present invention relates generally to a method and apparatus for inspecting a semiconductor wafer having a plurality of semiconductor devices such as Large Scale Integrated circuits (LSI). More particularly, this invention relates to an inspection method and inspection apparatus which performs a plurality of inspections on semiconductor devices with measuring probes contacting the semiconductor devices in order to determine whether or not the semiconductor devices on the wafer are defective.
2. Description of the Related Art
Typically, semiconductor devices formed on wafer materials undergo inspection before being assembled with other devices to form finished products. Ideally, only those semiconductor devices which have been detected as having been good are used in later assembly processes. This improves the yield economics of the semiconductor devices at the time they are packaged and shipped from the factory. Inspecting semiconductors in this fashion is usually done using measuring probes that come in contact with the semiconductor devices. During the inspection's execution a number of criteria are used to test the various semiconductor devices. These criteria, or inspection items comprise a check list against which the semiconductor devices are tested. For example, there are several hundreds to several thousands semiconductor devices on a single wafer, and about 20 to 30 inspection items used during the inspection of each semiconductor device. Consequently, the wafer inspection takes a considerable amount of time. Various methods have been proposed to shorten the wafer inspection time while keeping the yield of the semiconductor devices as high as possible. Such methods include a way of selectively inspecting some of the entire semiconductor devices (selective inspection) and thereby reducing the number of criteria or inspection items used in testing the semiconductor devices.
For example, Japanese Unexamined Patent Publication No. 61-216439 discloses a first wafer inspection method which selectively uses both a full and selective inspection process depending on the particular wafer region being inspected. This method is used due to the fact that different areas of the wafer typically have varying numbers of defects. According to this method, a full inspection is applied to the wafer's peripheral portion which has a statistically high probability of defect occurrence. A selective inspection is performed on the wafer's center which typically has a low probability of defect occurrence.
Japanese Unexamined Patent Publication No. 4-65143 discloses a second wafer inspection method in which the number of inspection criteria or items used during the inspection changes depending on the particular wafer region being inspected. This method, like that disclosed in the 61-216439 publication, utilizes the fact that various wafer regions have differing probabilities of containing defects. This particular inspection method executes a full inspection in the wafer's peripheral portion where a statistically high probability exists for the occurrence of defects, with respect to all of inspection criteria. In the wafer's center region, where the probability of occurrence of defects is relatively low, this inspection method first inspects a predetermined number of semiconductor devices using all of the inspection criteria. When all the inspected semiconductor devices are determined as adequate, subsequent semiconductor devices are inspected with a limited number of the preselected inspection criteria. If any defective semiconductor device is found in this partial inspection, then all subsequent semiconductor devices are inspected using all of the preselected inspection criteria.
Both of the above described first and second inspection methods unfortunately assume that the probability of defect occurrence is higher in the wafer's peripheral portion than it is in the wafer's center portion. In fact, the location of defects on a wafer depends on the fabrication process used to produce the semiconductor. In some cases regions other than the wafer's peripheral portion have the highest probability of containing defects. Typically, defect occurrence is concentrated in specific wafer areas such as the wafer's peripheral or center portion. None the less, defects can occur on any portion of the wafer due to minute foreign matters or inadequate washing. It is often times therefore difficult to specify the probable locations of defects.
When the occurrence of defects is concentrated in the wafer's center portion, some defects may go undetected by the first and second inspection methods. Specifically, when the first inspection method executes a selective inspection in the wafer's center portion, it may not detect certain defects that may in fact exist in the center region. Moreover, according to the second inspection method, when all of a predetermined number of semiconductor devices inspected first have passed the inspection, subsequent semiconductor devices are inspected using only some of the predetermined inspection criteria. Should defects exist of a type not detectable by the predetermined inspection criteria, those defects end up being determined as non-defects, or in other words, as good devices. In addition, if defects do exist among the predetermined number of semiconductor devices inspected first, the second inspection method executes an inspection routine using all of the inspection criteria thereafter. This inhibits the possibility of shortening the wafer inspection time.
Due to the above mentioned difficulties in specifying the probable locations of defects in semiconductor wafers, the first and second inspection methods are subject to overlooking existing defects. Consequently both methods have a tendency to reduce the yield of packaged semiconductor devices at the time of their factory shipment.